The invention relates to integrated circuit memories, and more particularly, to non-volatile type memories known under the acronyms EPROM for Electrically Programmable Read Only Memory, EEPROM for Electrically Erasable and Programmable Read Only Memory, and FLASH for a memory which is erasable in groups of memory cells. In such non-volatile memories, the invention relates to a method and device for checking the electrical state of reference cells used for reading, and for refreshing their electrical state as required.
A non-volatile type memory comprises a plurality of memory cells (FIG. 1) CE11, CE12, CE13, CE21, CE22 and CE23 which are arranged at the intersections of lines L1, L2 and columns C1, C2, C3. Each memory cell CE comprises an insulated gate MOSFET transistor having a drain D connected to a column, and a source S connected to ground and a gate G connected to a line. To erase the memory cell, the source S is connected to a high voltage, such as 12 volts, for example.
Information is stored based upon an electrical charge stored under the gate G. This charge is formed by electrons or holes. The storage of these charges is obtained by applying appropriate voltages on the electrodes D, S and G of each cell using circuits not shown in FIG. 1. The memory cell therefore exhibits two states: one without an electrical charge and the other with an electrical charge. The states respectively correspond, by convention, to a binary 1 and a binary 0.
Readout of the memory cells is achieved by applying other appropriate voltages on the electrodes D, S and G of each cell such that the signal supplied by a charged cell on the column is different from that supplied by a non-charged cell. By comparing the readout signal with that supplied by a reference cell, with the reference cell corresponding to a non-charged cell, a determination can be made as to whether the read memory cell is charged or not.
More specifically, the drain/source current Id (FIG. 2) of a memory cell varies as a function of the voltage VG applied to the gate G according to curve EFFA in the erased state (without charge), and according to curve PROG in the programmed state (charged). Curve A shown in dotted lines belongs to the reference cell and corresponds to a non-charged memory cell, but whose output signal is applied to an amplifier whose gain is less than one.
During a readout operation, a gate voltage VG1 is applied, which is between the two curves EFFA and PROG, and a measurement is made of the current Id1 of cell CE and the current Iref of the reference cell. If Id1 is less than Iref1, the memory cell is in the charged or programmed state (curve PROG). If Id1 is greater than Iref1, the memory cell is in the non-charged or erased state (curve EFFA).
The reference cells are produced in the form of an additional column REF of the memory such that a reference cell is called upon at each readout of a memory cell of the line. As a result of being called upon, the reference cell has a tendency to be charged each time, which causes its characteristic curve to become displaced towards the PROG curve. When this displacement is too great (curve E), a readout error results since the charged cell supplies a current Id2 greater than the current Iref2. This results in the cell being considered in the erased state, whereas the cell is actually in the programmed state. This error can appear after a short or long period of time depending on the characteristics of the reference cell, and the number of times the latter is called upon.
In view of the foregoing background, an object of the present invention is to avoid readout errors in a non-volatile memory due to a change in characteristics or a drift in the reference cell.
This and other objects, advantages and features according to the present invention are achieved by refreshing the electrical state of first degree reference cells when their drift exceeds a certain threshold determined by one or more other reference cells (second degree reference cells). The second degree reference cells can also be refreshed when their drift exceeds another threshold determined by one or more reference cells (third degree reference cells).
A device for refreshing at least one reference memory cell according to the invention is implemented in a recurrent manner, for example, at regular time intervals such as every year, or after a certain number of memory readout operations. The refresh of the reference cells can be achieved in different ways, either by their erasure or by a shift in their characteristic curve, or by a modification in the gain of the readout amplifier.
The invention also relates to a method of refreshing at least one reference memory cell in a non-volatile memory. The reference cell exhibits a characteristic curve which corresponds to a characteristic curve of an erased memory cell, but is shifted towards the characteristic curve of a programmed memory cell.
The method comprises the following steps:
(a) selecting at least a first non-used memory cell as a checking cell, and positioning its characteristic curve between that of the reference cell and that of a programmed cell;
(b) simultaneously reading a reference cell and the checking cell;
(c) comparing the signals read in step (b); and
(d) supplying a refresh signal for refreshing the selected reference cell when the signal read on the latter is less than the signal read on the checking cell.
When several reference cells are to be refreshed, step (d) is followed by the following step:
(e) returning to step (b) for another reference cell.
The refresh signal effects the characteristic curve of the reference cell in different ways: by erasing it, by performing a voltage shift in the reference cell, or by modifying the gain of the readout amplifier for the selected reference cell.
The device for refreshing at least one reference memory cell in a non-volatile memory includes a reference cell exhibiting a characteristic curve which corresponds to a characteristic curve of an erased memory cell, but is shifted towards the characteristic curve of a programmed memory cell. The device comprises means for selecting a non-used memory cell as a checking cell, and positioning the latter according to a characteristic curve arranged between that of the reference cell and that of a programmed cell. There are also means for simultaneously reading a reference cell and the checking cell.
The device further comprises means for comparing the signals read on the reference cell and on the checking cell, and supplying a refresh signal for refreshing the reference cell when the signal read on the reference cell is less than the signal read on the checking cell. There are means for modifying, in the presence of the refresh signal, the characteristic curve of the reference cell to return it substantially to its initial state.